System verilog support

[manbub]

Hi I am using this tool for systemverilog but would like to know how much information is added to the database. Tree-sitter parses alot of information from the code, what is being pulled out into the database. I have been playing with it and it's good but sometimes it says it can't trace signals from point it point? Thus the question.

[cookesan]

For SystemVerilog, I would set expectations in two layers.

The indexer does have a SystemVerilog grammar/spec. The current spec extracts things like:

functions/tasks
modules/classes/interfaces/packages/types
function and method calls
package imports, includes, instances
parameters and localparams

So the database should contain useful structural information from the files.

What it does not appear to have is a full HDL elaboration/dataflow engine. SystemVerilog is also not in the current full Hybrid LSP list, so cross-file type-aware resolution is not at the same level as Python, TypeScript, Go, C/C++, Java, Kotlin, Rust, etc.

That means "trace this signal from point A to point B" can fail even when parsing worked, especially if the path depends on module elaboration, generate blocks, interface/modport wiring, macros, parameterized instances, or nontrivial hierarchy.

One thing worth checking: the current built-in extension table maps .sv under the "SystemVerilog + Verilog" comment, but the actual enum used there is CBM_LANG_VERILOG. There is a separate CBM_LANG_SYSTEMVERILOG spec, so if your files are mostly .sv, they may currently be going through the Verilog path by default.

So my read is:

Supported: parsing/indexing useful structure from HDL files.
Not guaranteed: complete signal-level traceability across elaborated hardware hierarchy.
Possible issue: .sv may be routed as Verilog by the default extension mapping.

If you can share one small .sv example where tracing fails, it should be possible to tell whether it is an extension-detection problem or a missing relationship in the extractor.

[manbub]

Thank you that makes sense , as a hardware language signal reading is important where in other languages not as much. Let me try that and I will respond back next week.

[mdiamond-intel]

I have been playing with it for a week or so. using some coding, and some AI help I was able to get it to add overloading the trace_path tool, to trace signals. the big issue there is no preprocessing the code, so defines are not propagated across files, as well as only the files required to be loaded are not done it loads in all my verilog code i.e. stubs etc. so this is going to be a little more work than I thought. first thing is I need a preprocessor for any type of real code. any suggestions would be welcome!

[manbub]

Ok, system verilog is a harder language do to it's need to be preprocessed, I am working to introduce slang to preprocess the code before giving it to the parser, like c does. Also you.xam just read in random files to get anything usuefull you need to give it a top module and configuration switches used other wise the agent will have a hard time due to the links might be wrong. Will let you know how far I get

[DeusData]

Thank you for the SystemVerilog experiments, and sorry this did not receive a maintainer reply sooner. The comments identify a concrete need for preprocessing, a top module, and configuration-aware signal relationships; I cannot confirm complete signal tracing or a chosen Slang integration from this discussion. If you have a small shareable example now, please include the defines/top module and the expected signal path. That is enough to frame a focused request without asking you to build a full integration first.