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Xiongmai selects a pad's function with one enable bit per alternative in the
GPIO block at 0x10020000, all clear meaning GPIO:
- XM530/XM550: in the pad's own register, bits 1-3 (MUX1..MUX3);
- XM510: in its port's word of eight pins, bits b, 8 + b and 16 + b.
That is HiSilicon's shape -- one register, one field, every row a plain
read-modify-write -- so reginfo --pads and gpio mux now work on both. Pads
are numbered as the vendor does: GPIO N on XM530, port * 8 + pin on XM510
("8_1", "GPIO8_1"). XM530 refuses HiSilicon's "5_2", which would land on
pad 42.
Xiongmai publishes no table of what MUX1..3 carry, so rows are named FUNC1,
FUNC2 and FUNC3, except where the vendor's own code names them:
- XM530's SPI flash pads 9..14 (FLASH_*) and SD pads 43..50 and 52
(SDIO0_*);
- XM510's SD and Wi-Fi slots (SDIO1 on 5_0..5_3, SDIO2 on 6_0..6_3).
xm_detect_cpu() now sets chip_generation to CHIP_XM510 or CHIP_XM530, so
the front door can pick the backend.
Checked on a lab XM510 and a lab XM550:
- reginfo --pads agreed with every mux register read through devmem (all 100
pads on XM550, compared by script);
- gpio mux set and cleared exactly the pad's own bits, keeping XM550's
drive-strength bits.
reginfo_test decodes those boards' registers at rest and sweeps both tables.
PR Summary by QodoAdd Xiongmai pad-mux support for XM510 and XM530/XM550
AI Description
Diagram
High-Level Assessment
Files changed (8)
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Code Review by Qodo
1.
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…kend without the HAL Review of the first cut. - Pad names were written into shared buffers on first lookup. include/ipchw.h promises lookups read only constant data and may run concurrently, so they are now fixed-width const tables built at compile time. - xm_detect_cpu() gave every Xiongmai name but XM510 the XM530 layout. It now sets a generation for exactly XM510 and XM530 (XM550 is that die), and any other part keeps 0, so pad mux reports no table rather than writing registers on a layout nobody checked. - The backend is compiled into libipchw only when the Xiongmai HAL is: only that HAL sets the generations that reach it. Every camera's libipchw is built with the default 'all' tables, and without this each non-Xiongmai one would have carried code nothing can call. Measured as the firmware builds it (shared, -Os) on arm32: ipcinfo is unchanged for IPCHW_VENDORS=none, sstar and ingenic, and xm_padmux.o is absent from their libipchw.a. Xiongmai's own ipcinfo grows 102 bytes.
What
A pad-mux backend for Xiongmai, so that
reginfo --padsandgpio muxwork on XM510 and XM530/XM550.Both parts select a pad's function with one enable bit per alternative in the GPIO block at
0x10020000. All bits clear means GPIO.0x10020000 + 4 * pad, pads 0..99GPIO_MUX1_EN..3in the vendor'splatform.h)0x10020000 + 4 * port, ports 0..8b's bitsb,8 + b,16 + bThat's HiSilicon's shape with a bit per function instead of a selector nibble: one register and one field, and every row a plain read-modify-write. The backend is
src/hal/xm_padmux.c, behind a newxmfamily inIPCHW_PADMUX_FAMILIES.xm_detect_cpu()now setschip_generation(CHIP_XM510,CHIP_XM530), which the front door needs to pick a backend at all.Pads are numbered as the vendor does:
GPIO N. The HiSilicon5_2is refused, because it would land on pad 42.port * 8 + pin, written8_1orGPIO8_1.Names
Xiongmai publishes no table of what MUX1..3 carry on each pad, so rows are
FUNC1,FUNC2andFUNC3. The exceptions are pads where the vendor's own code says what it puts there, which carry its names:FLASH_CLK..FLASH_HOLD, fromplatform.handxmsfc_v2.c.SDIO0_*, fromsdio0_sd.c.5_0..5_3:SDIO1, fromsdio1_sd.c.6_0..6_3:SDIO2, fromsdio2_wifi.c.docs/padmux.mdlists what's deliberately left unnamed, and why.Tested
Host:
reginfo_testdecodes the two lab boards' registers at rest. It checks writes keep the rest of the word, and checks the pad spellings. Both tables join the integrity sweep and round trip. All tests pass.Lab XM510 + JX-H62:
reginfo --padsagreed with every port's mux word read throughdevmem:0_4/0_5and1_0/1_2on their 2nd function;1_4/1_5on their 3rd;5_0..5_3asSDIO1;7_0on its 1st.gpio mux 3_0 FUNC1set port 3's bit 0 only, andgpio mux 3_0 GPIOcleared it.gpio mux GPIO8_1resolved pad 65, and9_0was refused.Lab XM550: all 100 pads agreed with their registers, compared by script. The flash pads show as
FLASH_*and the SD pads asSDIO0_*.gpio mux 6 FUNC2wrote0x4andGPIOcleared it.gpio mux 51 FUNC3took pad 51 from0x80(8 mA drive) to0x88and back.5_2and100were refused.Size on cameras that aren't Xiongmai
The backend is compiled into
libipchwonly when the Xiongmai HAL is (IPCHW_VENDORScontainingxm, orall). It's reachable only through theCHIP_XM*generations, which only that HAL sets. Theipctoolexecutable carries it as it carries every table.Measured on arm32 the way the firmware builds it (shared,
SKIP_VERSION,-Os),ipcinfotext + data + bss, master → this branch:IPCHW_VENDORSipcinfoxm_padmux.oinlibipchw.anone(HiSilicon/Goke cameras)sstaringenicxmallNot changed here: those same non-Xiongmai
libipchw.abuilds still carry the SigmaStar, Ingenic and Novatek backends, becauseIPCHW_PADMUXdefaults toalland the firmware doesn't set it. The same vendor gate would trim them, as a separate change.