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ip-core

Here are 41 public repositories matching this topic...

vyges / vyges-ip-template

🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation

template opensource asic hardware systemverilog ip-core openlane hardware-ip vyges silicon-design

Updated Apr 30, 2026
Python

esynr3z / pip-hdl

📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

python vhdl verification vip pip verilog systemverilog ip-core rtl-design

Updated Jan 26, 2024
Python

Paebbels / pyIPCMI

A Python-based IP Core Management Infrastructure.

infrastructure database simulation vhdl intel python3 xilinx synthesis altera modelsim questasim xilinx-vivado quartus-prime vhdl-verification ip-core riviera-pro

Updated Apr 29, 2021
Python

iDoka / ipyxact

Python-based IP-XACT parser

asic fpga xml eda spirit rtl asciidoc ip verilog ip-xact soc vlsi uvm ip-core design-automation accellera ieee-1685 ieee1685

Updated Mar 27, 2017
Python

alohaic / spi_sensor_ctrl

Parameterizable SPI master IP core with APB interface, verified with cocotb on Verilator.

fpga rtl spi systemverilog yosys verilator apb ip-core cocotb

Updated Sep 25, 2026
Python

Tape-Out / uart

UART with a 16550-compatible register profile and a native profile

serial open-hardware rtl bluespec uart peripheral ip-core

Updated Sep 21, 2026
Python

Tape-Out / crc

Configurable CRC engine

open-hardware rtl crc bluespec peripheral ip-core

Updated Sep 21, 2026
Python

Tape-Out / erouter

Layer-3 forwarding engine with longest-prefix match

router networking routing ipv4 open-hardware rtl bluespec ethernet ip-core

Updated Oct 13, 2026
Python

Tape-Out / onew

1-Wire master

open-hardware rtl bluespec 1-wire peripheral ip-core

Updated Sep 21, 2026
Python

Tape-Out / ps2

PS/2 keyboard and mouse interface

input open-hardware rtl bluespec ps2 peripheral ip-core

Updated Sep 21, 2026
Python

Tape-Out / dma

DMA controller, with scatter-gather as a feature

open-hardware rtl bluespec dma peripheral ip-core

Updated Sep 21, 2026
Python

Tape-Out / lcdc

Display controller

display open-hardware rtl bluespec peripheral ip-core lcdc

Updated Sep 28, 2026
Python

Tape-Out / mbox

Inter-core mailbox

ipc open-hardware rtl bluespec mailbox peripheral ip-core

Updated Sep 21, 2026
Python

Tape-Out / rcu

Reset and clock unit

clock open-hardware rtl bluespec reset peripheral ip-core

Updated Sep 21, 2026
Python

Tape-Out / wdt

Windowed watchdog timer

open-hardware rtl bluespec watchdog peripheral ip-core

Updated Sep 21, 2026
Python

Tape-Out / picorv32

YosysHQ's PicoRV32 taken as a black box, with every parameter as a knob

cpu open-hardware riscv rtl verilog picorv32 ip-core

Updated Oct 12, 2026
Python

Tape-Out / sdhci

SD host controller

storage open-hardware rtl bluespec sdcard sd ip-core

Updated Sep 21, 2026
Python

Tape-Out / i2c

I2C master and slave, 7-bit and 10-bit addressing

i2c open-hardware rtl bluespec peripheral ip-core

Updated Sep 21, 2026
Python

Tape-Out / sdram

SDR SDRAM controller

memory open-hardware rtl bluespec dram ip-core sdram

Updated Sep 21, 2026
Python

tylrcc / tapeline

A small piece of FPGA hardware that works out live price averages (moving average and VWAP) as trades come in, so the trading software doesn't have to.

fpga dsp verilog quant algorithmic-trading icarus-verilog hardware-acceleration moving-average ip-core vwap

Updated Jun 1, 2026
Python

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