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The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Mar 25, 2026
Python

siliconcompiler / siliconcompiler

Star

Modular hardware build system

asic fpga hls vhdl eda rtl verilog make synthesis cmos

Updated Oct 21, 2026
Python

eldraco / Salamandra

Star

Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.

python threshold microphone sound rtl sdr microphones spy spy-microphones salamandra find-microphones detect-microphones

Updated Jan 11, 2021
Python

pymtl / pymtl3

Star

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

python rtl verilog systemverilog hdl open-source-hardware pymtl hardware-generation open-source-eda multi-level-modeling cycle-level-modeling

Updated Sep 10, 2026
Python

Eriemon / verilog-generator

Star

Agent skill for Verilog-2001 RTL generation and FPGA design workflows.

fpga eda rtl verilog hardware-generation claude-skills codex-skills agent-skill gemini-skills deepseek-harness-skills

Updated Aug 25, 2026
Python

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.

python rtl hdl pyrtl

Updated Oct 13, 2026
Python

Tencent / wave-mcp

Star

Open-source, license-free MCP server for RTL waveform debug: reads FST waveforms (VCD/FSDB auto-convert) plus a SystemVerilog netlist, with 34 tools covering driver analysis, value/X tracing, pass-fail waveform diff, a browser wave viewer the agent drives, and pre-simulation static analysis.

mcp waveform eda rtl debug vcd fst fsdb llm-tools chip-verification pyslang

Updated Oct 20, 2026
Python

Nic30 / hwt

Star

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

simulator fpga compiler hls vhdl rtl verilog hcl codegenerator codegen systemverilog systemc uvm

Updated Oct 16, 2026
Python

ics-jku / wal

Star

WAL enables programmable waveform analysis.

hardware vhdl verification eda rtl verilog vcd fst

Updated Sep 22, 2026
Python

gokeshenzhen / TraceWeave

Star

Open-source, evidence-driven MCP server for RTL simulation debugging: correlate VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM source, hierarchy, and connectivity to trace failures to root cause.

Updated Oct 13, 2026
Python

PrincetonUniversity / AutoSVA

Star

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

design verification rtl verilog systemverilog sva methodology-development